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| s Product Brief SCARABAEUS SDA 9400 Scanrate Converter Using Embedded Dram Technology Units Potential Application The SDA 9400 is a new component of the Siemens MEGAVISION(R)IC set for building high end TV sets 100/120 Hz interlaced TV sets 50/60 Hz Progressive Scan TV sets Features Two Input Data Formats - 4:2:2 luminance and chrominance parallel (2 x 8 wires) - ITU-R 656 data format (8 wires) Flexible Compression of the Input Signal - Digital vertical compression of the input signal (1.0, 1.25, 1.5, 1.75, 2.0, 3.0, 4.0) - Digital horizontal compression of the input signal (1.0, 2.0, 4.0) Noise Reduction - Motion adaptive spatial and temporal noise reduction (3DNR) - Flexible programming of the temporal noise reduction parameters - Automatic measurement of the noise level (5 bit value, readable by I 2C Bus) 3-D Motion Detection SCARABAEUS - High performance motion detector for scan rate conversion - Global motion detection flag (readable by I 2C Bus) - Movie mode and phase detector (readable by I 2C Bus) Embedded Memory 5 Mbit Embedded DRAM Core for Field Memories, 192 kbit Embedded DRAM Core for Line Memories Flexible Clock and Synchronization Concept Scan Rate Conversion - Motion adaptive 100/120 Hz interlaced scan conversion - Motion adaptive 50/60 Hz progressive scan conversion - Simple static interlaced and progressive conversion modes for 100/120 Hz interlaced or 50/60 Hz progressive scan conversion: e. g. ABAB, AABB, AA*B*B, AAAA, BBBB, AB, AA* - Large area and line flicker reduction Flexible Digital Vertical Expansion of the Output Signal (1.0, ... [1/32]..., 2.0) Flexible Output Sync Controller Signal Manipulations - Insertion of coloured background - Vertical and/or horizontal windowing with four different speed factors - Flash generation (for supervising applications, motion flag readable by I 2C Bus) - Still frame or field - Support for split screen applications (PIP processor necessary) - Still-in-moving picture, Movingin-still picture (PIP processor http://www.siemens.de/semiconductor/ Technical Data I 2 C Bus control (400 kHz) P-MQFP-64 package 3.3 V 5% supply voltage 0.35 m CMOS technology 4:2:2 processing Block Diagram SDA 9400 Embedded memory - 5 Mbit embedded DRAM core for field memories - 192 kbit embedded DRAM core for line memories Availability The SDA 9400 and a complete documentation is available in samples 1998. Mass production is scheduled for 1999. A dedicated engineering support team is there to assist you. Also an application board is available. Please contact your local Siemens office for further ISC Input sync controller MC Memory Controller ED eDRAM Interfaces Data buffer Voltage control Test controller OSC Output sync controller A Wien (+43) 1-1707-35611 Richmond (Melbourne), Vic. 3121 (+61) 3-94207111 Brussel/Bruxelles (+32) 2-536 23 48 IRL Dublin 4 (+353) 1-603 23 48 Tokyo 141-0022 (+81) 3-5449 64 Penang (+60) 4-644 9975 Oslo 5 (+47) 22-63 30 00 Den Haag (+31) 70-333 24 29 Auckland (+64) 9-520 3033 Amadora (+35) 1-4170011 Islamabad (+92) 51-2122 00 Warszawa (+48) 2-670 9151 Taipei (+886) 2-25237990 Seoul 135-080 (+82) 2-527 77 00 Moskva (+7) 095-237-6476, -6911 Kista (+46) 8-703 35 00 Singapore 349 253 (+65) 840 0610 Findikli (Istanbul) (+90) 212-25109 00 Cupertino, CA 95014 (+1) 408-777 45 00 Cupertino, CA 95014 (+1) 408-257 7910 Iselin, NJ 08830-2770 (+1) 732-906 43 00 Beijing (+86) 10-6857 90 -06, -07 Shanghai 200003 (+86) 21-63612618/19 Halfway House 1685 (+27) 11-652 -2000, -2700 AUS IFC Input format conversion LDR Vertical, Horizontal decimation Noise reduction and measurement Motion detector J HDR Scan rate conversion Vertical interpolation MAL OFC output format conversion B N BR Sao Paulo-SP (+55) 11-836 2547 NL CDN I 2C I 2C Bus Interface Motion mode and phase detection LM Line memory Mississauga, Ontario L5T 1P2 (+1) 905-819 80 00 Zurich (+41) 1-495 3111 Dusseldorf (+49) 211-39915 51 Laatzen (Hannover) (+49) 511-8772706 Nurnberg (+49) 911-65476 22 Stuttgart (+49) 711-137 3314 Munchen (+49) 89-922140 86 Ballerup (+45) 4477-4477 NZ PLL 1 Clock doubling PLL 2 Clock doubling LM Line memory CH P D PK PL The SDA 9400 is a single core IC for 100 Hz containing all necessary blocks RC The SDA 9400 contains all necessary functional blocks on a single chip: Flexible input sync controller Input format conversion Low data rate processing Memory controller Flexible output sync controller Application Example Output format conversion High data rate processing I 2C Bus interface PLL for frequency doubling and in a leading edge technology 5.2 Mbit embedded DRAM for line and field memories. ROK DK RUS E Tres Cantos-Madrid (+34) 1-514 80 00 Saint-Denis CEDEX 2 (+33) 1-4922 3100 Espoo (Helsinki) (+35) 9-51051 Berkshire RG 12 8FZ (+44) 1344-39 60 00 Amaroussio/Athen (+30) 1-686 4111 Hong Kong (+852) 2832 05 00 Milano (+39) 2-6676-1 New Delhi 110 014 (+91) 11-46174 47 Bangalore 560 001 (+91) 80-2279874 Mumbai 18 (+91) 22-496 2199 VRC S F FIN SGP GB TR GR USA HK Y Analog colour decoder + RGB input SDA 9206 ABACUS YUVIN 8 SDA 9400 SCARABAEUS Y 8 UV 8 HOUT, VOUT, HREF CLKOUT SDA 9280 Displayprocessor Y I U HIN1 U IND CVBS V SYNC VIN1 CLK1=27MHz V ZA How to reach us: R G B H-Drive http://www.siemens.de/semiconductor/ address/address.htm (c) Siemens AG 1998. CVBS PIP processor e.g. SDA 9488 SDA 936X Deflection controller All Rights Reserved. V-Drive E/W Please note that any information contained in this publication may be subject to change. Siemens reserves the right to make changes to or to discontinue any product or service identified in this publication without notice. Please contact our regional offices to receive the latest version of the relevant information to verify, before placing orders, that the information being relied upon is current. Application of a 100 Hz TV set Published by Semiconductor Group Siemens Aktiengesellschaft Ordering No. B110-H7217-X-X-7600 Printed in Germany PS 05983. 1102980029 |
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